Bugs fixes in "intel-microcode"
Origin | Bug number | Title | Date fixed |
---|---|---|---|
CVE | CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially enable denia | 2024-08-19 |
CVE | CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged use | 2024-08-19 |
CVE | CVE-2023-43490 | Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow a privileged user to potential | 2024-05-29 |
CVE | CVE-2023-22655 | Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privilege | 2024-05-29 |
CVE | CVE-2023-28746 | Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may all | 2024-05-29 |
CVE | CVE-2023-38575 | Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to potentially enable i | 2024-05-29 |
CVE | CVE-2023-39368 | Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to potentially enable denial of ser | 2024-05-29 |
CVE | CVE-2023-47855 | Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially enable escalat | 2024-05-29 |
CVE | CVE-2023-45745 | Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially enable escalat | 2024-05-29 |
CVE | CVE-2023-46103 | Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an authenticated user to potentially | 2024-05-29 |
CVE | CVE-2023-45733 | Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enable partial information disclos | 2024-05-29 |
CVE | CVE-2023-43490 | Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow a privileged user to potential | 2024-05-29 |
CVE | CVE-2023-22655 | Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privilege | 2024-05-29 |
CVE | CVE-2023-28746 | Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may all | 2024-05-29 |
CVE | CVE-2023-38575 | Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to potentially enable i | 2024-05-29 |
CVE | CVE-2023-39368 | Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to potentially enable denial of ser | 2024-05-29 |
CVE | CVE-2023-47855 | Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially enable escalat | 2024-05-29 |
CVE | CVE-2023-45745 | Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially enable escalat | 2024-05-29 |
CVE | CVE-2023-46103 | Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an authenticated user to potentially | 2024-05-29 |
CVE | CVE-2023-45733 | Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enable partial information disclos | 2024-05-29 |
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