Bugs fixes in "intel-microcode"
| Origin | Bug number | Title | Date fixed |
|---|---|---|---|
| CVE | CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially enable denia | 2024-08-19 |
| CVE | CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged use | 2024-08-19 |
| CVE | CVE-2023-49141 | Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of privilege v | 2024-08-19 |
| CVE | CVE-2023-42667 | Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable escalation o | 2024-08-19 |
| CVE | CVE-2024-24980 | Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escal | 2024-08-19 |
| CVE | CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially enable denia | 2024-08-19 |
| CVE | CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged use | 2024-08-19 |
| CVE | CVE-2023-49141 | Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of privilege v | 2024-08-19 |
| CVE | CVE-2023-42667 | Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable escalation o | 2024-08-19 |
| CVE | CVE-2024-24980 | Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escal | 2024-08-19 |
| CVE | CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially enable denia | 2024-08-19 |
| CVE | CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged use | 2024-08-19 |
| CVE | CVE-2023-49141 | Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of privilege v | 2024-08-19 |
| CVE | CVE-2023-42667 | Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable escalation o | 2024-08-19 |
| CVE | CVE-2024-24980 | Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escal | 2024-08-19 |
| CVE | CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially enable denia | 2024-08-19 |
| CVE | CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged use | 2024-08-19 |
| CVE | CVE-2023-49141 | Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of privilege v | 2024-08-19 |
| CVE | CVE-2023-42667 | Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable escalation o | 2024-08-19 |
| CVE | CVE-2024-24980 | Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escal | 2024-08-19 |
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